SoC Design Front-end, Digital Engineers (Junior/Senior/Principal)

About NSING:

As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry.

Our products includes General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low Energy BLE and BMS (Battery Management System).

When you join NSING, you will be part of a talented team in the Singapore R&D Center where we develop high performance MCU targeting for Industrial and Edge AI applications.

Key Responsibilities

1. RTL Design

Develop and implement synthesizable RTL code using Verilog/SystemVerilog based on system and micro-architecture specifications.

Design digital blocks such as I2C, XSPI, datapaths, DMA controllers and high-performance industrial standards interfaces and buses.

2. Architecture & Micro-architecture

Participate in defining micro-architecture and design specifications.

Evaluate trade-offs between performance, power, and area (PPA).

3. Functional Verification Support

Able to build self-test environment to verify the key functionality of IP before handling over to the verification engineer.

Collaborate with verification engineers to create test plans and ensure complete coverage.

Support simulation, debugging, and root-cause analysis of design issues.

4. Design Integration

Integrate IP blocks and ensure correct functionality within the SoC environment, define clear constraint for your IP.

Work closely with architect, RTL2GLN, and backend design teams to ensure.

5. Synthesis & Linting

Run synthesis and static checks such as linting, CDC (Clock Domain Crossing), and reset domain checks.

Ensure RTL quality meets design guidelines and coding standards like spyglass checks.

6. Documentation

Prepare design documentation including micro-architecture specifications, block diagrams, and design reports.

Maintain clear version control and design traceability.

7. Cross-functional Collaboration

Work with backend engineers for timing closure and design optimization.

Support silicon bring-up, debugging, and post-silicon validation when required.

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

3 to 5 years of experience in digital IC design (entry-level roles may accept fresh graduates).

Strong knowledge of digital design fundamentals (FSM, pipelining, clocking, reset strategies).

Proficiency in Verilog/SystemVerilog RTL design.

Experience with simulation and debugging tools.

Understanding of ASIC/SoC design flow.

Preferred Qualifications

Experience with EDA tools such as Synopsys, Cadence, or Siemens EDA tools.

Familiarity with low power design techniques (UPF/CPF).

Knowledge of DFT (Design for Test) concepts.

Experience integrating standard interfaces such as AXI, AHB, SPI, I2C, or PCIe.

Basic scripting skills (Python, Perl, or TCL).

Key Competencies

Strong analytical and debugging skills

Attention to detail in digital logic design

Ability to work in cross-functional engineering teams

Good documentation and communication skills